Since High Bandwidth Memory (HBM) has been certified by JEDEC (the body that sets official memory specifications), we saw the first memory chip of its kind in 2013, manufactured by SK Hynix.
After the first generation, the second generation of HBM2 was launched in 2016, and the second generation was updated in 2018. Therefore, the manufacturer relied on HBM2E memory, then relied on HBM3 memory, and released HBM3 memory. In 2020, the updated version of HBM3E will be released in 2023.
High-bandwidth memory (HBM) is primarily used to accelerate high-performance computing (HPC) and is used by large companies like NVIDIA and AMD with a variety of graphics processors.
Today, the South Korean giant Samsung announced that the company's HBM4 memory has reached an advanced stage, taking performance to the next level. This statement was made by Mr. Sang Joon Hwang, Executive Vice President and Head of the DRAM Product Team at Samsung. Meanwhile, Samsung has confirmed that it will soon make HBM3E storage, which offers a data transfer rate of 9.8/s and bandwidth of up to 1.25 TB/s per packet, available to its customers and AI and edge applications. . Energy accounting ecosystem.
In the statement, Sang emphasized the integration of technologies with high thermal properties, including non-conductive chip assembly (NCF) and hybrid copper bonding (HCB), with hybrid bonding providing a solution to achieve higher bandwidth, higher performance and improved signal integrity and performance. Ability to stack individual packages, as with the 16-Hi package version.
In addition to the storage benefits of HBM4, including a 2048 bits per packet storage interface (versus 1024 bits per packet in HBM3), we're also talking about achieving 2 TB/s per packet, versus 1.2 TB/s. per package. From HBM3E. per package.
The non-conductive chip component (NCF) is a polymer layer to protect the TSV. TSV is a technology that connects the top and bottom chips through thousands of tiny holes that direct data, instructions, and power along vertical paths that penetrate the entire thickness of the silicon chip once the chips are stacked. Multiple DRAM modules are stacked on top of each other on insulating chips; This results in high transfer speeds and optimal communication between stacked chips.
This process allows for a size reduction of up to 30% and a reduction of energy consumption of up to 50% through the wafer packing method. In addition, HCB technology uses copper conductors and thin insulating layers instead of traditional soldering, effectively reducing the gap and providing access to 2048-bit memory interfaces.
Samsung's announcement indicated a specific timetable for the launch of HBM4 memories in 2025, but the production phase is expected to begin between 2025 and 2026 for mass production, which is what happened with Micron, which is preparing to launch its own memories in 2025. Storage version 2025. Name of the period ( HBMNext). Ditto in various capacities.